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AD9833的技术资料

来源：深圳创盛电子有限公司发布时间：2009/4/16 15:44:02

AD9833的产品特征：
●+2.3 V to +5.5 V Power Supply
●25 MHz Speed
●Tiny 10-Pin μμμμμSOIC Package
●Serial Loading
●Sinusoidal/Triangular DAC Output
●Power-Down Option
●Narrowband SFDR > 72 dB
●20 mW Power Consumption at 3 V

AD9833的技术参数：

Parameter	Min	Typ	Max	Units	Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS Resolution Update Rate (f_MAX) Output Compliance² DC Accuracy: Integral Nonlinearity Differential Nonlinearity		10 ±1 ±0.5	25 0.8	Bits MSPS V LSB LSB
DDS SPECIFICATIONS Dynamic Specifications: Signal to Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range (SFDR): Wideband (± 2 MHz) NarrowBand (± 50 kHz) Clock Feedthrough Wake Up Time	50 50 55 72 75	–55 1	-53	dB dBc dBc dBc dBc dBc dBc ms	f_MCLK = 25 MHz, fOUT = 1.5 kHz f_MCLK = 25 MHz, fOUT = 1.5 kHz f_MCLK = 25 MHz, fOUT = fMCLK/3 f_MCLK = 25 MHz, fOUT = 0.5 MHz f_MCLK= 25 MHz, fOUT = fMCLK/3 f_MCLK = 25 MHz, fOUT = 0.5 MHz
OUTPUT BUFFER Output Rise/Fall Time Output Jitter		20 100		ns ps rms	Using a 15 pF Load When DAC data MSB is output
VOLTAGE REFERENCE Internal Reference	1.116	1.2	1.284	V	1.2 V ± 7%
LOGIC INPUTS V_INH, Input High Voltage V_INL, Input Low Voltage I_INH, Input Current C_IN, Input Capacitance	VDD –0.9 VDD - 0.5 2		0.9 0.5 1 10	V V V V V μA pF	+3.6 V to +5.5 V Power Supply +2.7 V to +3.6 V Power Supply +2.3 V to + 2.7 V Power Supply +3.6 V to +5.5 V Power Supply +2.3 V to + 3.6 V Power Supply
POWER SUPPLIES VDD I_AA³ I_DD³ IAA + I_DD³ Low Power Sleep Mode3	2.3	1 + 0.04/MHz 7 10 0.25	5.5 5 10 15	V mA mA mA mA mA	f_MCLK = 25 MHz, f_OUT = f_MCLK/7 3 V Power Supply 5 V Power Supply DAC and Internal Clock Powered Down

AD9833的产品描述：

This low power DDS device is a numerically controlled oscillator employing a phase accumulator, a SIN ROM and a 10-bit D/A converter integrated on a single CMOS chip. Clock rates up to 25 MHz are supported with a power supply from +2.3 V to +5.5 V.

Capability for phase modulation and frequency modula-tion is provided. Frequency accuracy can be controlled to one part in 0.25 billion. Modulation is effected by loading registers through the serial interface.

The AD9833 offers a variety of output waveforms from the VOUT pin. The SIN ROM can be bypassed so that a linear up/down ramp is output from the DAC. If the SIN ROM is not by-passed, a sinusoidal output is available.Also, if a clock output is required, the MSB of the DAC data can be output.

The digital section is internally operated at +2.5 V, irre-spective of the value of VDD, by an on board regulator which steps down VDD to +2.5 V, when VDD exceeds+2.5 V.

The AD9833 has a power-down function (SLEEP). This allows sections of the device which are not being used to be powered down, thus minimising the current consump-tion of the part e.g the DAC can be powered down when a clock output is being generated. The AD9833 is available in a 10-pin μSOIC package.